module transfer(
  input        io_systemclk,
  input        io_systemRstn,
  input  [1:0] io_cardio_card_group_data,
  input        io_cardio_card_group_cmd,
  output       io_cardio_group_card_state,
  output [7:0] io_cardio_group_card_result,
  output [1:0] io_emitterio_fpga_cim_data,
  output       io_emitterio_fpga_cim_cmd,
  input        io_emitterio_cim_fpga_state,
  input  [7:0] io_emitterio_cim_fpga_result
);
  wire  systemRst = ~io_systemRstn; // @[transfer.scala 31:19]
  reg [1:0] io_emitterio_fpga_cim_data_r; // @[Reg.scala 28:20]
  reg  io_emitterio_fpga_cim_cmd_r; // @[Reg.scala 28:20]
  reg [7:0] io_cardio_group_card_result_r; // @[Reg.scala 28:20]
  reg  io_cardio_group_card_state_r; // @[Reg.scala 28:20]
  assign io_cardio_group_card_state = io_cardio_group_card_state_r; // @[transfer.scala 36:34]
  assign io_cardio_group_card_result = io_cardio_group_card_result_r; // @[transfer.scala 35:34]
  assign io_emitterio_fpga_cim_data = io_emitterio_fpga_cim_data_r; // @[transfer.scala 33:32]
  assign io_emitterio_fpga_cim_cmd = io_emitterio_fpga_cim_cmd_r; // @[transfer.scala 34:32]
  always @(posedge io_systemclk) begin
    if (systemRst) begin // @[Reg.scala 28:20]
      io_emitterio_fpga_cim_data_r <= 2'h0; // @[Reg.scala 28:20]
    end else begin
      io_emitterio_fpga_cim_data_r <= io_cardio_card_group_data;
    end
    if (systemRst) begin // @[Reg.scala 28:20]
      io_emitterio_fpga_cim_cmd_r <= 1'h0; // @[Reg.scala 28:20]
    end else begin
      io_emitterio_fpga_cim_cmd_r <= io_cardio_card_group_cmd;
    end
    if (systemRst) begin // @[Reg.scala 28:20]
      io_cardio_group_card_result_r <= 8'h0; // @[Reg.scala 28:20]
    end else begin
      io_cardio_group_card_result_r <= io_emitterio_cim_fpga_result;
    end
    if (systemRst) begin // @[Reg.scala 28:20]
      io_cardio_group_card_state_r <= 1'h0; // @[Reg.scala 28:20]
    end else begin
      io_cardio_group_card_state_r <= io_emitterio_cim_fpga_state;
    end
  end
endmodule
